Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

997

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with the 16-bit mode of the 
LCD controller.

The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) 
through a Programmable Clock output or by an external oscillator connected to the sensor.

None of the sensors embed a power management controller, so providing the clock by the APMC is a simple and efficient 
way to control power consumption of the system.

Care must be taken when programming the system clock. The ISI has two clock domains, the sensor master clock and 
the pixel clock provided by sensor. The two clock domains are not synchronized, but the sensor master clock must be 
faster than the pixel clock.

RGB 5:6:5

Byte 0

G2(i)

G1(i)

G0(i)

R4(i)

R3(i)

R2(i)

R1(i)

R0(i)

Byte 1

B4(i)

B3(i)

B2(i)

B1(i)

B0(i)

G5(i)

G4(i)

G3(i)

Byte 2

G2(i+1)

G1(i+1)

G0(i+1)

R4(i+1)

R3(i+1)

R2(i+1)

R1(i+1)

R0(i+1)

Byte 3

B4(i+1)

B3(i+1)

B2(i+1)

B1(i+1)

B0(i+1)

G5(i+1)

G4(i+1)

G3(i+1)

RGB 8:8:8

Byte 0

R0(i)

R1(i)

R2(i)

R3(i)

R4(i)

R5(i)

R6(i)

R7(i)

Byte 1

G0(i)

G1(i)

G2(i)

G3(i)

G4(i)

G5(i)

G6(i)

G7(i)

Byte 2

B0(i)

B1(i)

B2(i)

B3(i)

B4(i)

B5(i)

B6(i)

B7(i)

Byte 3

R0(i+1)

R1(i+1)

R2(i+1)

R3(i+1)

R4(i+1)

R5(i+1)

R6(i+1)

R7(i+1)

RGB 5:6:5

Byte 0

G3(i)

G4(i)

G5(i)

R0(i)

R1(i)

R2(i)

R3(i)

R4(i)

Byte 1

B0(i)

B1(i)

B2(i)

B3(i)

B4(i)

G0(i)

G1(i)

G2(i)

Byte 2

G3(i+1)

G4(i+1)

G5(i+1)

R0(i+1)

R1(i+1)

R2(i+1)

R3(i+1)

R4(i+1)

Byte 3

B0(i+1)

B1(i+1)

B2(i+1)

B3(i+1)

B4(i+1)

G0(i+1)

G1(i+1)

G2(i+1)