Atmel SAM4S Xplained Pro Starter Kit Atmel ATSAM4S-XSTK ATSAM4S-XSTK Data Sheet

 195

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

SCB_CCR

Access: Read-write

Reset: 0x000000000

The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated 
by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to the 
NVIC_STIR register by unprivileged software (see 

).

Indicates the stack alignment on exception entry:

0: 4-byte aligned.

1: 8-byte aligned. 

On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the exception, it 
uses this stacked bit to restore the correct stack alignment.

Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault 
and FAULTMASK escalated handlers:

0: Data bus faults caused by load and store instructions cause a lock-up.

1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.

Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system 
devices and bridges to detect control path problems and fix them. 

Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:

0: Do not trap divide by 0.

1: Trap divide by 0. 

When this bit is set to 0, a divide by zero returns a quotient of 0.

Enables unaligned access traps:

0: Do not trap unaligned halfword and word accesses.

1: Trap unaligned halfword and word accesses. 

31

30

29

28

27

26

25

24

–

23

22

21

20

19

18

17

16

–

15

14

13

12

11

10

9

8

–

STKALIGN

BFHFNMIGN

7

6

5

4

3

2

1

0

–

DIV_0_TRP

UNALIGN_TRP

–

USERSETMPE

ND

NONBASETHR

DENA