Atmel SAM4S Xplained Pro Starter Kit Atmel ATSAM4S-XSTK ATSAM4S-XSTK Data Sheet
Product codes
ATSAM4S-XSTK
335
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
22.
Cortex M Cache Controller (CMCC) (ONLY FOR SAM4SD32/SD16/SA16)
22.1
Description
The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a
tag directory, data memory, metadata memory and a configuration interface.
tag directory, data memory, metadata memory and a configuration interface.
22.2
Embedded Characteristics
Physically addressed and physically tagged
L1 data cache set to 2 Kbytes
L1 cache line size set to 16 Bytes
L1 cache integrates 32-bit bus master interface
Unified Direct mapped cache architecture
Unified 4-Way set associative cache architecture
Write through cache operations, read allocate
Round Robin victim selection policy
Event Monitoring, with one programmable 32-bit counter
Configuration registers accessible through Cortex M Private Peripheral Bus
Cache Interface includes cache maintenance operations registers
22.3
Block Diagram
Figure 22-1. Block Diagram
Cache
Controller
Controller
METADATA RAM
DATA RAM
TAG RAM
RAM
Interface
Interface
Cortex M Interface
Memory Interface
Registers
Interface
Interface
APB
Interface
Interface
Cortex M Memory Interface Bus
System Memory Bus