Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

107

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

to indicate that the main clock comes from OSC8M. The GCLK_MAIN clock source can be selected again by writing a 
zero to the CTRL.BKUPCLK bit. Writing the bit does not fix the failure, however.

Note 1: The detector does not monitor while the main clock is temporarily unavailable (startup time after a wake-up, etc.) 
or in sleep mode. The Clock Failure Detector must be disabled before entering standby mode.

Note 2: The clock failure detector must not be enabled if the source of the main clock is not significantly faster than the 
OSCULP32K clock. For instance, if GCLK_MAIN is the internal 32kHz RC, then the clock failure detector must be 
disabled.

Note 3: The OSC8M internal oscillator should be enabled to allow the main clock switching to the OSC8M clock.

The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to 
determine proper action.

There are two groups of reset sources:

z

Power Reset: Resets caused by an electrical issue.

z

User Reset: Resets caused by the application.

The table below lists the parts of the device that are reset, depending on the reset type.

The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to 
be driven externally during normal operation.

The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller 
Interface (SYSCTRL).

The WDT reset is generated by the Watchdog Timer.

The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the 
SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM

®

 Cortex

®

http://www.arm.com

).

RTC
All the 32kHz sources
WDT with ALWAYSON feature
Generic Clock with WRTLOCK 
feature

Y

N

N

Debug logic

Y

Y

N

Others

Y

Y

Y