Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
182
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
17.6.3 Additional Features
17.6.3.1 Always-On Mode
The always-on mode is enabled by writing a one to the Always-On bit in the Control register (CTRL.ALWAYSON). When
the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the
Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control
(EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration
bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the
Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control
(EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration
bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling window-mode operation by writing the Window Enable bit (CTRL.WEN) is allowed while in the
always-on mode, but note that CONFIG.PER cannot be changed.
always-on mode, but note that CONFIG.PER cannot be changed.
The Interrupt Clear and Interrupt Set registers are accessible in the always-on mode. The Early Warning interrupt can still
be enabled or disabled while in the always-on mode, but note that EWCTRL.EWOFFSET cannot be changed.
be enabled or disabled while in the always-on mode, but note that EWCTRL.EWOFFSET cannot be changed.
shows the operation of the WDT when CTRL.ALWAYSON is set.
Table 17-2. WDT Operating Modes With Always-On
17.6.4 Interrupts
The WDT has the following interrupt sources:
z
Early Warning
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the WDT is reset. See
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the WDT is reset. See
for details on how to clear interrupt flags.
The WDT has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to
The Early Warning interrupt behaves differently in normal mode and in window mode. In normal mode, the Early Warning
interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET).
The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the
start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and
EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the
watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the
start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If
these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog
time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be
generated.
interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET).
The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the
start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and
EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the
watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the
start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If
these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog
time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be
generated.
WEN
Interrupt enable
Mode
0
0
Always-on and normal mode
0
1
Always-on and normal mode with Early Warning interrupt
1
0
Always-on and window mode
1
1
Always-on and window mode with Early Warning interrupt