Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
189
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
17.8.3 Early Warning Interrupt Control
Name:
EWCTRL
Offset:
0x2
Reset:
N/A - Loaded from NVM User Row at startup
Property:
Write-Protected, Enable-Protected
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – EWOFFSET[3:0]: Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period
to when the Early Warning interrupt is generated. The Early Warning Offset is defined in
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period
to when the Early Warning interrupt is generated. The Early Warning Offset is defined in
. These bits
are loaded from NVM User Row at startup. Refer to
for more details.
Bit
7
6
5
4
3
2
1
0
EWOFFSET[3:0]
Acces
s
s
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
X
X
X
X
Table 17-5. Early Warning Interrupt Time Offset
Value
Description
0x0
8 clock cycles
0x1
16 clock cycles
0x2
32 clock cycles
0x3
64 clock cycles
0x4
128 clock cycles
0x5
256 clocks cycles
0x6
512 clocks cycles
0x7
1024 clock cycles
0x8
2048 clock cycles
0x9
4096 clock cycles
0xA
8192 clock cycles
0xB
16384 clock cycles
0xC-0xF
Reserved