Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
244
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
19.6.7 Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in
CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin
EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx.
CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin
EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx.
Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended.
Figure 19-3. Wake-Up Operation Example (High-Level Detection, No Filter, WAKEUPEN[x]=1)
19.6.8 Synchronization
Due to the asynchronicity between CLK_EIC_APB and GCLK_EIC, some registers must be synchronized when
accessed. A register can require:
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control register (CTRL.SWRST)
z
Enable bit in the Control register (CTRL.ENABLE)
No register needs synchronization when written.
No register needs synchronization when read.
CLK_EIC_APB
EXTINTx
intwake_extint[x]
intreq_extint[x]
clear INTFLAG.EXTINT[x]
return to sleep mode