Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
273
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
20.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x0C
Reset:
0x00
Property:
Write-Protected
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled
0: Error interrupt is disabled
1: Error interrupt is enabled
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
z
Bit 0 – READY: NVM Ready Interrupt Enable
0: NVM Ready interrupt is disabled
0: NVM Ready interrupt is disabled
1: NVM Ready interrupt is enabled
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the NVM Ready Interrupt Enable bit, which disables the NVM Ready interrupt.
Bit
7
6
5
4
3
2
1
0
ERROR
READY
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0