Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

281

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

 for details on the pin mapping for this peripheral. One signal 

can be mapped on several pins. 

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

The I/O lines of the PORT are mapped to pins of the physical device package according to a simple naming scheme. 
Each line bundle of up to 32 pins is assigned a letter identifier, starting with A, that monotonically increases through the 
alphabet for each subsequent line bundle. Within each line bundle, each pin is assigned a numerical identifier according 
to its bit position.

The resulting PORT pins are mapped as Pxy, where x=A, B, C,… and y=00, 01, …, 31 to uniquely identify each pin in the 
device, e.g., PA24, PC03, etc.

Each pin may have one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated 
peripheral function. When enabled, the selected peripheral is given control over the output state of the pad, as well as the 
ability to read the current physical pad state. Refer to 

Device-specific configurations may result in some pins (and the corresponding Pxy pin) not being implemented.

PORTMUX

ANALOG

BLOCKS

PERIPHERALS

Digital Controls of Analog Blocks

Analog Pad
Connections

I/O

PADS

Port Line 

Bundles

IP Line Bundles

Peripheral Mux Select

PORT

Control

and

Status

Pad Line 

Bundles

Pxy

Digital I/O

General-purpose I/O pin y