Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
323
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
22.8.5 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x10
Reset:
0x00000000
Property:
Write-Protected
z
Bits 31:16 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 15:8 – EVDx: Event Detected Channel x Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event
Detected Channel x interrupt.
Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event
Detected Channel x interrupt.
z
Bits 7:0 – OVRx: Overrun Channel x Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
1: The Overrun Channel x interrupt is enabled.
0: The Overrun Channel x interrupt is disabled.
1: The Overrun Channel x interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
EVD7
EVD6
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OVR7
OVR6
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0