Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the 
following registers: 

z

Interrupt Flag Status and Clear register (INTFLAG)

z

Address register (ADDR) 

z

Data register (DATA) 

Write-protection is denoted by the Write-Protection property in the register description. 

When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to 

Not applicable.

The basic structure of the SERCOM serial engine is shown in 

synchronous to the system clock and accessible by the CPU, while fields with lowercase letters can be configured to run 
on the  GCLK_SERCOMx_CORE clock or an external clock.

The transmitter consists of a single write buffer and a shift register. The receiver consists of a two-level receive buffer and 
a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external 
clock. Address matching logic is included for SPI and I

2

C operation.

 

 

 

 

 

 

 

 

 

 

Transmitter

Baud Rate Generator

= =

Selectable

Internal Clk

(GCLK)

Ext Clk

Receiver

Address Match

baud rate generator

tx shift register

rx shift register

rx buffer

status

BAUD

TX DATA

ADDR/ADDRMASK

RX DATA

STATUS

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