Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
341
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z
Communication mode (asynchronous or synchronous) must be selected by writing to the Communication Mode bit
in the Control A register (CTRLA.CMODE)
in the Control A register (CTRLA.CMODE)
z
SERCOM pad to use for the receiver must be selected by writing to the Receive Data Pinout bit group in the
Control A register (CTRLA.RXPO)
Control A register (CTRLA.RXPO)
z
SERCOM pads to use for the transmitter and external clock must be selected by writing to the Transmit Data
Pinout bit in the Control A register (CTRLA.TXPO)
Pinout bit in the Control A register (CTRLA.TXPO)
z
Character size must be selected by writing to the Character Size bit group in the Control B register
(CTRLB.CHSIZE)
(CTRLB.CHSIZE)
z
MSB- or LSB-first data transmission must be selected by writing to the Data Order bit in the Control A register
(CTRLA.DORD)
(CTRLA.DORD)
z
When parity mode is to be used, even or odd parity must be selected by writing to the Parity Mode bit in the Control
B register (CTRLB.PMODE) and enabled by writing 0x1 to the Frame Format bit group in the Control A register
(CTRLA.FORM)
B register (CTRLB.PMODE) and enabled by writing 0x1 to the Frame Format bit group in the Control A register
(CTRLA.FORM)
z
Number of stop bits must be selected by writing to the Stop Bit Mode bit in the Control B register
(CTRLB.SBMODE)
(CTRLB.SBMODE)
z
When using an internal clock, the Baud register (BAUD) must be written to generate the desired baud rate
z
The transmitter and receiver can be enabled by writing ones to the Receiver Enable and Transmitter Enable bits in
the Control B register (CTRLB.RXEN and CTRLB.TXEN)
the Control B register (CTRLB.RXEN and CTRLB.TXEN)
24.6.2.2 Enabling, Disabling and Resetting
The USART
is enabled by writing a one to the Enable bit in the Control A
register (CTRLA.ENABLE). The USART is
disabled by writing a zero to CTRLA.ENABLE.
The USART
is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the USART, except DBGCTRL, will be reset to their initial state, and the USART will be disabled. Refer to the CTRLA
register for details.
register for details.
24.6.2.3 Clock Generation and Selection
For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated
internally by the SERCOM baud-rate generator or supplied externally through the XCK line. Synchronous mode is
selected by writing a one to the Communication Mode bit in the Control A register (CTRLA.CMODE) and asynchronous
mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the
Operation Mode bit group in the Control A register (CTRLA.MODE) and the external clock source is selected by writing
0x0 to CTRLA.MODE.
internally by the SERCOM baud-rate generator or supplied externally through the XCK line. Synchronous mode is
selected by writing a one to the Communication Mode bit in the Control A register (CTRLA.CMODE) and asynchronous
mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the
Operation Mode bit group in the Control A register (CTRLA.MODE) and the external clock source is selected by writing
0x0 to CTRLA.MODE.
. When CTRLA.CMODE is zero, the baud-rate
generator is automatically set to asynchronous mode and the 16-bit Baud register value is used. When CTRLA.CMODE
is one, the baud-rate generator is automatically set to synchronous mode and the eight LSBs of the Baud register are
used. Refer to
is one, the baud-rate generator is automatically set to synchronous mode and the eight LSBs of the Baud register are
used. Refer to
for details on configuring the baud rate.