Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
352
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.8.2 Control B
Name:
CTRLB
Offset:
0x04
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
0: The receiver is disabled or being enabled.
1: The receiver is enabled or will be enabled when the USART is enabled.
Writing a zero to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and
clear the FERR, PERR and BUFOVF bits in the STATUS register.
clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing a one to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART
is enabled, CTRLB.RXEN will be cleared, and STATUS.SYNCBUSY will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as one.
is enabled, CTRLB.RXEN will be cleared, and STATUS.SYNCBUSY will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the USART is enabled will set STATUS.SYNCBUSY, which will remain set
until the receiver is enabled, and CTRLB.RXEN will read back as one.
until the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
z
Bit 16 – TXEN: Transmitter Enable
0: The transmitter is disabled or being enabled.
0: The transmitter is disabled or being enabled.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RXEN
TXEN
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PMODE
SFDE
Access
R
R
R/W
R
R
R
R/W
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SBMODE
CHSIZE[2:0]
Access
R
R/W
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0