Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
364
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
25.5.7 Debug Operation
When the CPU is halted in debug mode, the SPI continues normal operation. If the SPI is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The SPI can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL)
register for details.
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The SPI can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL)
register for details.
25.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
following registers:
z
Interrupt Flag Clear and Status register (
)
z
)
z
Data register (
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to
25.5.9 Analog Connections
Not applicable.
25.6
Functional Description
25.6.1 Principle of Operation
The SPI is a high-speed synchronous data transfer interface. It allows fast communication between the device and
peripheral devices.
peripheral devices.
The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions. The SPI is single
buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with
the next character to be transmitted while the current transmission is in progress. For receiving, this means that the data
is transferred to the two-level receive buffer upon reception, and the receiver is ready for a new character.
buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with
the next character to be transmitted while the current transmission is in progress. For receiving, this means that the data
is transferred to the two-level receive buffer upon reception, and the receiver is ready for a new character.
The SPI transaction format is shown in
, where each transaction can contain one or more characters. The
character size is configurable, and can be either 8 or 9 bits.
Figure 25-2. SPI Transaction Format
The SPI master must initiate a transaction by pulling low the slave select line (_SS) of the desired slave. The master and
slave prepare data to be sent in their respective shift registers, and the master generates the serial clock on the SCK line.
Data are always shifted from master to slave on the master output, slave input line (MOSI), and from slave to master on
the master input, slave output line (MISO). The master signals the end of the transaction by pulling the _SS line high.
slave prepare data to be sent in their respective shift registers, and the master generates the serial clock on the SCK line.
Data are always shifted from master to slave on the master output, slave input line (MOSI), and from slave to master on
the master input, slave output line (MISO). The master signals the end of the transaction by pulling the _SS line high.
As each character is shifted out from the master, another character is shifted in from the slave.
Character
Transaction
MOSI/MISO
_SS
Character 0
Character 1
Character 2