Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
377
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
25.8.2 Control B
Name:
CTRLB
Offset:
0x04
Reset:
0x00000000
Property:
Write-Protected, Enable-Protected
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
0: The receiver is disabled or being enabled.
1: The receiver is enabled or it will be enabled when SPI is enabled.
Writing a zero to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing a one to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is
enabled, CTRLB.RXEN will be cleared, STATUS.SYNCBUSY will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as one.
enabled, CTRLB.RXEN will be cleared, STATUS.SYNCBUSY will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the SPI is enabled will set STATUS.SYNCBUSY, which will remain set until
the receiver is enabled, and CTRLB.RXEN will read back as one.
the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RXEN
Access
R
R
R
R
R
R
R/W
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
AMODE[1:0]
Access
R/W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PLOADEN
CHSIZE[2:0]
Access
R
R/W
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0