Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
415
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.8.1.6 Status
Name:
STATUS
Offset:
0x10
Reset:
0x0000
Property:
-
z
Bit 15 – SYNCBUSY: Synchronization Busy
This bit is set when the synchronization of registers between clock domains is started.
This bit is set when the synchronization of registers between clock domains is started.
This bit is cleared when the synchronization of registers between the clock domains is complete.
z
Bits 14:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 7 – CLKHOLD: Clock Hold
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I
2
C
clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INT-
FLAG.AMATCH is set.
FLAG.AMATCH is set.
This bit is automatically cleared when the corresponding interrupt is also cleared.
z
Bit 6 – LOWTOUT: SCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
or when INTFLAG.AMATCH is cleared.
0: No SCL low time-out has occurred.
1: SCL low time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
z
Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 4 – SR: Repeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
0: Start condition on last address match
1: Repeated start condition on last address match
This flag is only valid while the INTFLAG.AMATCH flag is one.
Bit
15
14
13
12
11
10
9
8
SYNCBUSY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CLKHOLD
LOWTOUT
SR
DIR
RXNACK
COLL
BUSERR
Access
R
R/W
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0