Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
428
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.8.2.6 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x0D
Reset:
0x00
Property:
Write-Protected
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – SB: Slave on Bus Interrupt Enable
0: The Slave on Bus interrupt is disabled.
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus interrupt.
z
Bit 0 – MB: Master on Bus Interrupt Enable
0: The Master on Bus interrupt is disabled.
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt.
Bit
7
6
5
4
3
2
1
0
SB
MB
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0