Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
432
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.8.2.9 Address
Name:
ADDR
Offset:
0x14
Reset:
0x0000
Property:
Write-Synchronized
z
Bits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – ADDR[7:0]: Address
When ADDR is written, the consecutive operation will depend on the bus state:
When ADDR is written, the consecutive operation will depend on the bus state:
Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
Busy: The I
2
C master will await further operation until the bus becomes idle.
Idle: The I
2
C master will issue a start condition followed by the address written in ADDR. If the address is acknowl-
edged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start
is performed while INTFLAG.MB or INTFLAG.SB is set.
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start
is performed while INTFLAG.MB or INTFLAG.SB is set.
Regardless of winning or losing arbitration, the entire address will be sent. If arbitration is lost, only ones are trans-
mitted from the point of losing arbitration and the rest of the address length.
mitted from the point of losing arbitration and the rest of the address length.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the master logic to perform any bus protocol related operations.
trigger the master logic to perform any bus protocol related operations.
The I
2
C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for
read.
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0