Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the 
pulse width and period. This can be used to characterize the frequency and duty cycle of an input signal:

When using PPW event action, the period (T) will be captured into CC0 and the pulse width (tp) in CC1. In PWP event 
action, the pulse width (tp) will be captured in CC0 and the period (T) in CC1.

Selecting PWP (pulse-width, period) or PPW (period, pulse-width) in the Event Action bit group in the Event Control 
register (EVCTRL.EVACT) enables the TC to performs two capture actions, one on the rising edge and one on the falling 
edge. 

The TC Inverted Event Input in the Event Control register (EVCTRL.TCINV) is used to select whether the wraparound 
should occur on the rising edge or the falling edge. If EVCTRL.TCINV is written to one, the wraparound will happen on 
the falling edge. The event source to be captured must be an asynchronous event.

To fully characterize the frequency and duty cycle of the input signal, activate capture on CC0 and CC1 by writing 0x3 to 
the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). When only one of these 
measurements is required, the second channel can be used for other purposes.

The TC can detect capture overflow of the input capture channels. When the Capture Interrupt flag is set and a new 
capture event is detected, there is nowhere to store the new timestamp. Asa result, INTFLAG.ERR is set.

When one-shot operation is enabled, the counter automatically stops on the next counter overflow or underflow 
condition. When the counter is stopped, STATUS.STOP is automatically set by hardware and the waveform outputs are 
set to zero.

One-shot operation can be enabled by writing a one into the One-Shot bit in the Control B Set register 
(CTRLBSET.ONESHOT) and disabled by writing a one to the One-Shot bit in the Control B Clear register 
(CTRLBCLR.ONESHOT). When enabled, it will count until an overflow or underflow occurs. The one-shot operation can 
be restarted with a retrigger command, a retrigger event or a start event.

When the counter restarts its operation, the Stop bit in the Status register (STATUS.STOP) is automatically cleared by 
hardware.

The TC has the following interrupt sources: 

z

Overflow/Underflow: OVF

z

Compare or Capture Channels

z

Capture Overflow Error: ERR

z

Synchronization Ready: SYNCRDY 

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 

1
T

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