Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
463
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
27.8.8 Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x0C
Reset:
0x00
Property:
Write-Protected
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – MCx: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
disables the Match or Capture Channel x interrupt.
z
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Syn-
chronization Ready interrupt.
chronization Ready interrupt.
z
Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 1 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt.
z
Bit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt.
Bit
7
6
5
4
3
2
1
0
MC1
MC0
SYNCRDY
ERR
OVF
Access
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0