Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
526
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
29.9
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to
the Write-Protected property in each individual register description. Refer to
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to
or the Read-Synchronized property in each individual register description. Refer to
for
details.
Some registers are enable-protected, meaning they can be written only when the AC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
denoted by the Enable-Protected property in each individual register description.
29.9.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
z
Bit 7 – LPMUX: Low-Power Mux
0: The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the
voltage doubler).
1: The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage dou-
bler is disabled).
0: The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the
voltage doubler).
1: The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage dou-
bler is disabled).
This bit are not synchronized
z
Bits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – RUNSTDBY: Run in Standby
This bit controls the behavior of the comparators during standby sleep mode.
This bit controls the behavior of the comparators during standby sleep mode.
0: The comparator pair is disabled during sleep.
1: The comparator pair continues to operate during sleep.
1: The comparator pair continues to operate during sleep.
This bit is not synchronized
z
Bit 1 – ENABLE: Enable
0: The AC is disabled.
0: The AC is disabled.
1: The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator
Control register (COMPCTRLn.ENABLE).
Control register (COMPCTRLn.ENABLE).
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value
written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is set. STA-
TUS.SYNCBUSY is cleared when the peripheral is enabled/disabled.
written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is set. STA-
TUS.SYNCBUSY is cleared when the peripheral is enabled/disabled.
Bit
7
6
5
4
3
2
1
0
LPMUX
RUNSTDBY
ENABLE
SWRST
Access
R/W
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0