Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
530
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
29.9.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x04
Reset:
0x00
Property:
Write-Protected
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – WIN0: Window 0 Interrupt Enable
Reading this bit returns the state of the Window 0 interrupt enable.
Reading this bit returns the state of the Window 0 interrupt enable.
0: The Window 0 interrupt is disabled.
1: The Window 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Window 0 interrupt.
z
Bits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – COMPx: Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Reading this bit returns the state of the Comparator x interrupt enable.
0: The Comparator x interrupt is disabled.
1: The Comparator x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Comparator x interrupt.
Bit
7
6
5
4
3
2
1
0
WIN0
COMP1
COMP0
Access
R
R
R
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0