Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

connected to the DAC, the enabled action will be taken on any of the incoming events. Refer to 

 for details on configuring the event system.

The generic clock for the DAC is running in idle sleep mode. If the Run In Standby bit in the Control A register 
(CTRLA.RUNSTDBY) is one, the DAC output buffer will keep its value in standby sleep mode. If CTRLA.RUNSTDBY is 
zero, the DAC output buffer will be disabled in standby sleep mode.

Due to the asynchronicity between CLK_DAC_APB

 

and GCLK_DAC,

 

some registers must be synchronized when 

accessed. A register can require:

z

Synchronization when written

z

Synchronization when read

z

Synchronization when written and read

z

No synchronization

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register 
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization 
Ready interrupt can be used to signal when synchronization is complete.

If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All 
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is 
stalled.

The following bits need synchronization when written:

z

Software Reset bit in the Control A register (CTRLA.SWRST)

z

Enable bit in the Control A register (CTRLA.ENABLE)

z

All bits in the Data register (DATA)

z

All bits in the Data Buffer register (DATABUF)

Synchronization is denoted by the Write-Synchronized property in the register description.

The following bits need synchronization when read:

z

All bits in the Data register (DATA)