Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

Product codes
ATSAMD20-XPRO
Page of 660
554
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
30.8.6 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x6
Reset:
0x00
Property:
Write-Protected
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), 
except when the transition is caused by an enable or a software reset, and will generate an interrupt request if 
INTENCLR/SET.READY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready interrupt flag.
z
Bit 1 – EMPTY: Data Buffer Empty
This flag is cleared by writing a one to the flag or by writing new data to DATABUF.
This flag is set when data is transferred from DATABUF to DATA, and the DAC is ready to receive new data in 
DATABUF, and will generate an interrupt request if INTENCLR/SET.EMPTY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Buffer Empty interrupt flag.
z
Bit 0 – UNDERRUN: Underrun
This flag is cleared by writing a one to the flag.
This flag is set when a start conversion event occurs when DATABUF is empty, and will generate an interrupt 
request if INTENCLR/SET.UNDERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Underrun interrupt flag.
Bit
7
6
5
4
3
2
1
0
SYNCRDY
EMPTY
UNDERRUN
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0