Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
599
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
32.12.4 SWD Timing
Figure 32-15.SWD Interface Signals
Table 32-44. SWD Timings
Note:
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Symbol
Parameter
Conditions
Min.
Max.
Units
Thigh
SWDCLK High period
V
VDDIO
from 3.0V to 3.6V,
maximum external capacitor =
40pF
10
500000
ns
Tlow
SWDCLK Low period
10
500000
Tos
SWDIO output skew to falling edge
SWDCLK
SWDCLK
-5
5
Tis
Input Setup time required between
SWDIO
SWDIO
4
-
Tih
Input Hold time required between
SWDIO and rising edge SWDCLK
SWDIO and rising edge SWDCLK
1
-
Stop
Park
Tri State
Acknowledge
Tri State
Tri State
Parity
Start
Data
Data
Stop
Park
Tri State
Acknowledge
Tri State
Start
Read Cycle
Write Cycle
Tos
Thigh
Tlow
Tis
Data
Data
Parity
Tri State
Tih
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger