Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

Product codes
ATSAMD20-XPRO
Page of 660
625
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
o Wait for fine lock (PCLKSR.DFLLLCKF set to 1)
o Switch back system clock/module clocks to the DFLL48M
Better accuracy is achieved using a high multiplier for the DFLL48M, using a 
scaled down or slow clock as reference. A multiplier of 6 will have a theoretical 
worst case frequency deviation from the reference clock of +/- 8.33%. A multiplier 
of 500 will have a theoretical worst case frequency deviation from the reference 
clock of +/- 0.1%.
4 - If the DFLL48M reaches the maximum or minimum COARSE or FINE 
calibration values during the locking sequence, an out of bounds interrupt 
will be generated. These interrupts will be generated even if the final 
calibration values at DFLL48M lock are not at maximum or minimum, and 
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt 
Flag Status and Clear register (INTFLAG) are both set before enabling the 
DFLLOOB interrupt.
35.2.8 EVSYS
1 - Using synchronous or resynchronized paths, some channels (0,3,6,7) 
detect an overrun on every event even if no overrun condition is present. 
Errata reference: 10895
Fix/Workaround:
- Ignore overrun detection bit for channels 0,3,6,7.
- Use channels 1,2,4,5 if overrun detection is required.
2 - Changing the selected generator of a channel can trigger a spurious 
interrupt/event. Errata reference: 10443
Fix/Workaround:
To change the generator of a channel, first write with EDGESEL written to zero, 
then perform a second write with EDGESEL written to its target value.
35.2.9 SERCOM
1 - The SERCOM SPI CTRLA register bit 17 (DOPO Bit 1) will always be zero, 
and cannot be changed. Therefore the SERCOM SPI cannot be switched 
between master and slave mode on the same DI and DO pins.  Errata 
reference: 10812
Fix/Workaround:
Connect the alternate DI and DO pins externally and use the port MUX to switch 
between pin configurations for master and slave functionality.