Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

Product codes
ATSAMD20-XPRO
Page of 660
90
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
14.8.3 Generic Clock Control
This register allows the user to configure one of the generic clocks, as specified in the CLKCTRL.ID bit group. To write to 
the CLKCTRL register, do a 16-bit write with all configurations and the ID.
To read the CLKCTRL register, first do an 8-bit write to the CLKCTRL.ID bit group with the ID of the generic clock whose 
configuration is to be read, and then read the CLKCTRL register.
Name:
CLKCTRL
Offset:
0x2
Reset:
0x0000
Property:
Write-Protected
z
Bit 15 – WRTLOCK: Write Lock
When this bit is written, it will lock further writes to the generic clock pointed by the CLKCTRL.ID. The generic clock 
generator pointed by CLKCTRL.GEN and the GENDIV.DIV will also be locked.
One exception to this is generic clock generator 0, which cannot be locked.
0: The generic clock and the associated generic clock generator and division factor are not locked.
1: The generic clock and the associated generic clock generator and division factor are locked.
z
Bit 14 – CLKEN: Clock Enable
This bit is used to enable and disable a generic clock.
0: The generic clock is disabled.
1: The generic clock is enabled.
z
Bits 13:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – GEN[3:0]: Generic Clock Generator
These bits select the generic clock generator to be used as the source of a generic clock. The value of the GEN bit 
group versus generic clock generator is shown in 
Bit
15
14
13
12
11
10
9
8
WRTLOCK
CLKEN
GEN[3:0]
Access
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0