Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet
Product codes
ATSAM4L-XPRO
73
42023ES–SAM–07/2013
ATSAM4L8/L4/L2
8.7.14
JTAG Instructions
Refer to the ARM Debug Interface v5.1 Architecture Specification for more details on ABORT,
DPACC, APACC and IDCODE instructions.
DPACC, APACC and IDCODE instructions.
8.7.14.1
EXTEST
This instruction selects the boundary-scan chain as Data Register for testing circuitry external to
the chip package. The contents of the latched outputs of the boundary-scan chain is driven out
as soon as the JTAG IR-register is loaded with the EXTEST instruction.
the chip package. The contents of the latched outputs of the boundary-scan chain is driven out
as soon as the JTAG IR-register is loaded with the EXTEST instruction.
Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way:
1.
Select the IR Scan path.
2.
In Capture-IR: The IR output value is latched into the shift register.
3.
In Shift-IR: The instruction register is shifted by the TCK input.
4.
In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5.
Return to Run-Test/Idle.
6.
Select the DR Scan path.
7.
In Capture-DR: The data on the external pins is sampled into the boundary-scan chain.
8.
In Shift-DR: The boundary-scan chain is shifted by the TCK input.
9.
In Update-DR: The data from the scan chain is applied to the output pins.
10. Return to Run-Test/Idle.
8.7.14.2
SAMPLE_PRELOAD
This instruction takes a snap-shot of the input/output pins without affecting the system operation,
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Register.
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Register.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
DR Size
Shows the number of bits in the data register chain when this instruction is active.
Example: 32 bits
DR input value
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active.
instruction is active.
DR output value
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active.
instruction is active.
Table 8-4.
Instruction Description (Continued)
Instruction
Description
Table 8-5.
EXTEST Details
Instructions
Details
IR input value
0000 (0x0)
IR output value
p00s
DR Size
Depending on boundary-scan chain, see BSDL-file.
DR input value
Depending on boundary-scan chain, see BSDL-file.
DR output value
Depending on boundary-scan chain, see BSDL-file.