Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO Data Sheet

42023ES–SAM–07/2013

Application Test Environment Example 

To enable the JTAG pins a falling edge event must be detected on the TCK pin at any time after
the RESET_N pin is released. 

Certain operations requires that the system is prevented from running code after reset is
released. This is done by holding low the TCK pin after the RESET_N is released. This makes
the SMAP assert the core_hold_reset signal that hold the Cortex-M4 core under reset.

To make the CPU run again, clear the CHR bit in the Status Register (SR.CHR) to de-assert the
core_hold_reset signal. Independent of the initial state of the TAP Controller, the Test-Logic-
Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence
should always be applied at the start of a JTAG session and after enabling the JTAG pins  to
bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on
TMS for 1 TCK period brings the TAP Controller to the Run-Test/Idle state, which is the starting
point for JTAG operations.

To disable the JTAG pins the TCK pin must be held high while RESET_N pin is released.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register - Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions
into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input
must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG
Instruction selects a particular Data Register as path between TDI and TDO and controls the cir-
cuitry surrounding the selected Data Register.

Chip 2

Chip n

Chip 1

SAM4

SAM4-based Application Board In Test

JTAG

Connector

Tester

Test Adaptor

JTAG

Probe