Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
1003
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
40.3
Block Diagram
Figure 40-1.
Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing
8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48
MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is
then notified that the device asks for a resume. This optional feature must also be negotiated with the host during
the enumeration.
40.3.1 Signal Description
40.4
Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document.
Atmel Bridge
12 MHz
Suspend/Resume Logic
Serial
Interface
Engine
SIE
MCK
Master Clock
Domain
Domain
Dual
Port
RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
Domain
udp_int
(interrupt line)
(interrupt line)
USB Device
Embedded
USB
Transceiver
DDP
DDM
APB
to
MCU
Bus
txoen
eopn
txd
rxdm
rxd
rxdp
Wrapper
Wrapper
User
Interface
Table 40-2.
Signal Names
Signal Name
Description
Type
UDPCK
48 MHz clock
Input
MCK
Master clock
Input
udp_int
Interrupt line connected to the Interrupt Controller
Input
DDP
USB D+ line
I/O
DDM
USB D- line
I/O