Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

118

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax

op{S}{cond} {Rd,} Rn, Operand2

op{cond} {Rd,} Rn, #imm12

; ADD and SUB only

where:
opis one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
Sis an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see 

.

condis an optional condition code, see 

.

Rdis the destination register. If Rd is omitted, the destination register is Rn.
Rnis the register holding the first operand.
Operand2is a flexible second operand. See 

 for details of the

options.
imm12is any value in the range 0–4095.
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is 

reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide 

range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on.
See also 

.

Note:

ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses 

the imm12 operand.

Restrictions
In these instructions:



 must not be SP and must not be PC



 can be SP only in ADD and SUB, and only with the additional restrictions:

̶

 must also be SP

̶

Any shift in Operand2 must be limited to a maximum of 3 bits using LSL



 can be SP only in ADD and SUB



 can be PC only in the ADD{cond} PC, PC, Rm instruction where:

̶

The user must not specify the S suffix