Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax

op{cond} {Rd}, Rn, Rm

where:
opis any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
condis an optional condition code, see 

.

Rdis the destination register.
Rn, Rmare registers holding the first and second operands.
Operation
The SHASX instruction:

1. Adds the top halfword of the first operand with the bottom halfword of the second operand.

2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to 

the right causing a divide by two, or halving.

3. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit 

to the right causing a divide by two, or halving.

The SHSAX instruction:

1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.

2. Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit 

to the right causing a divide by two, or halving.

3. Adds the bottom halfword of the first operand with the top halfword of the second operand.
4. Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to 

the right causing a divide by two, or halving.

Restrictions
Do not use SP and do not use PC

Condition Flags
These instructions do not affect the condition code flags.