Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

133

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

where
condis an optional condition code, see 

.

Rnis the register holding the first operand.
Operand2is a flexible second operand. See 

 for details of the

options
Operation
These instructions test the value in a register against Operand2. They update the condition flags based on the 

result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the 

same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 

and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. 

This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the 

sign bits of the two operands.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:



Update the N and Z flags according to the result



Can update the C flag during the calculation of Operand2, see 



Do not affect the V flag.

Examples

TST

R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8, 

; APSR is updated but result is discarded

TEQEQ

R10, R9

; Conditionally test if value in R10 is equal to 

; value in R9, APSR is updated but result is discarded.

Unsigned Add 16 and Unsigned Add 8
Syntax

op{cond}{Rd,} Rn, Rm

where:
opis any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
condis an optional condition code, see 

.

Rdis the destination register.
Rnis the first register holding the operand.
Rmis the second register holding the operand.