Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

171

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Pack Halfword
Syntax

op{cond} {Rd}, Rn, Rm {, LSL #imm}

op{cond} {Rd}, Rn, Rm {, ASR #imm}

where:
opis one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
condis an optional condition code, see 

.

Rdis the destination register.
Rnis the first operand register
Rmis the second operand register holding the value to be optionally shifted.
immis the shift length. The type of shift length depends on the instruction:

For PKHBT

LSL a left shift with a shift length from 1 to 31, 0 means no shift.

For PKHTB

ASR an arithmetic shift right with a shift length from 1 to 32,

a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction: 

1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.

2. If shifted, the shifted value of the second operand is written to the top halfword of the destination register.

The PKHTB instruction:

1. Writes the value of the top halfword of the first operand to the top halfword of the destination register.

2. If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.

Restrictions

 must not be SP and must not be PC.

Condition Flags
This instruction does not change the flags.