Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

184



Do not branch to any instruction inside an IT block, except when returning from an exception handler



All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside 

an IT block but has a larger branch range if it is inside one



Each instruction inside the IT block must specify a condition code suffix that is either the same or logical 

inverse as for the other instructions in the block.

 

Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler 

directives within them.
Condition Flags
This instruction does not change the flags.
Example

ITTE

NE

; Next 3 instructions are conditional

ANDNE

R0, R0, R1

; ANDNE does not update condition flags

ADDSNE R2, R2, #1

; ADDSNE updates condition flags

MOVEQ

R2, R3

; Conditional move

CMP

R0, #9

; Convert R0 hex value (0 to 15) into ASCII 

; ('0'-'9', 'A'-'F')

ITE

GT

; Next 2 instructions are conditional

ADDGT

R1, R0, #55

; Convert 0xA -> 'A'

ADDLE

R1, R0, #48

; Convert 0x0 -> '0'

IT

GT

; IT block with only one conditional instruction

ADDGT

R1, R1, #1

; Increment R1 conditionally

ITTEE

EQ

; Next 4 instructions are conditional

MOVEQ

R0, R1

; Conditional move

ADDEQ

R2, R2, #10

; Conditional add

ANDNE

R3, R3, #1

; Conditional AND

BNE.W

dloop

; Branch instruction can only be used in the last

; instruction of an IT block

IT

NE

; Next instruction is conditional

ADD

R0, R0, R1

; Syntax error: no condition code used in IT block

Table Branch Byte and Table Branch Halfword.
Syntax

TBB [Rn, Rm]

TBH [Rn, Rm, LSL #1]

where:
Rnis the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately

following the TBB or TBH instruction.