Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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This section describes the NVIC and the registers it uses. The NVIC supports:



Up to 35 interrupts.



A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so 

level 0 is the highest interrupt priority.



Level detection of interrupt signals.



Dynamic reprioritization of interrupts.



Grouping of priority values into group priority and subpriority fields.



Interrupt tail-chaining.



An external Non-maskable interrupt (NMI)

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no 

instruction overhead. This provides low latency exception handling.

The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral 

deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear 

the interrupt request. 
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see 

). For a level-sensitive interrupt, if the signal is not deasserted before the 

processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR 

again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.

The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:



The NVIC detects that the interrupt signal is HIGH and the interrupt is not active



The NVIC detects a rising edge on the interrupt signal



A software writes to the corresponding interrupt set-pending register bit, see 

, or to the NVIC_STIR to make an interrupt pending, see 

.

A pending interrupt remains pending until one of the following:



The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. 

Then:

̶

For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the 

interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might 

cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to 

inactive.



Software writes to the corresponding interrupt clear-pending register bit.

For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not 

change. Otherwise, the state of the interrupt changes to inactive.

Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned 

accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from 

taking that interrupt.