Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, 

and memory attributes of each region. It supports:



Independent attribute settings for each region



Overlapping regions



Export of memory attributes to the system.

The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:



Eight separate memory regions, 0–7



A background region.

When memory regions overlap, a memory access is affected by the attributes of the region with the highest 

number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps 

region 7.
The background region has the same memory access attributes as the default memory map, but is accessible 

from privileged software only. 
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the 

same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory 

management fault. This causes a fault exception, and might cause the termination of the process in an OS 

environment. 
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be 

executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see 

).

 shows the possible MPU region attributes. These include Share ability and cache behavior attributes 

that are not relevant to most microcontroller implementations. See 

 for 

guidelines for programming such an implementation.

This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and 

XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of 

memory without the required permissions, then the MPU generates a permission fault.

Strongly-ordered

–

–

All accesses to Strongly-ordered memory occur in program order. All 

Strongly-ordered regions are assumed to be shared.

Device

Shared

–

Memory-mapped peripherals that several processors share. 

Non-shared

–

Memory-mapped peripherals that only a single processor uses.

Normal

Shared

Non-cacheable Write-

through Cacheable 

Write-back Cacheable

Normal memory that is shared between several processors.

Non-shared

Non-cacheable Write-

through Cacheable 

Write-back Cacheable

Normal memory that only a single processor uses.