Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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Exception

An event that interrupts program execution. When an exception occurs, the processor suspends the 

normal program flow and starts execution at the address indicated by the corresponding exception 

vector. The indicated address contains the first instruction of the handler for the exception. 
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults 

include attempting an invalid memory access, attempting to execute an instruction in an invalid 

processor state, and attempting to execute an undefined instruction.

Exception service routine

Exception vector

Flat address mapping

A system of organizing memory in which each physical address in the memory space is the same as 

the corresponding virtual address.

Halfword

A 16-bit data item.

Illegal instruction

An instruction that is architecturally Undefined.

Implementation-defined

The behavior is not architecturally defined, but is defined and documented by individual 

implementations.

Implementation-specific

The behavior is not architecturally defined, and does not have to be documented by individual 

implementations. Used when there are a number of implementation options available and the option 

chosen does not affect software compatibility.

Index register

In some load and store instruction descriptions, the value of this register is used as an offset to be 

added to or subtracted from the base register value to form the address that is sent to memory. Some 

addressing modes optionally enable the index register value to be shifted prior to the addition or 

subtraction. 
See also 

Instruction cycle count

The number of cycles that an instruction occupies the Execute stage of the pipeline.

Interrupt handler

A program that control of the processor is passed to when an interrupt occurs.

Interrupt vector

One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, 

that contains the first instruction of the corresponding interrupt handler.