Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

322

WDT_MR

0x400E1454

Read-write Once

 

Note: The first write access prevents any further modification of the value of this register, read accesses remain possible.
Note: The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog 

performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than 

expected.

Defines the value loaded in the 12-bit Watchdog Counter. 

0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.

0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.

0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

Defines the permitted range for reloading the Watchdog Timer. 
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. 
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.

0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.

31

30

29

28

27

26

25

24

WDIDLEHLT

WDDBGHLT

WDD

23

22

21

20

19

18

17

16

WDD

15

14

13

12

11

10

9

8

WDDIS

WDRPROC

WDRSTEN

WDFIEN

WDV

7

6

5

4

3

2

1

0

WDV