Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
346
19.
General-Purpose Backup Registers (GPBR)
19.1
Description
The System Controller embeds 8 General-purpose Backup registers.
It is possible to generate an immediate clear of the content of General-purpose Backup registers 0 to 3 (first half) if
It is possible to generate an immediate clear of the content of General-purpose Backup registers 0 to 3 (first half) if
a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other
General-purpose Backup registers (second half) remains unchanged.
The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply
The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply
Controller module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be
other than 0.
If a Tamper event has been detected, it is not possible to write to the General-purpose Backup registers while the
If a Tamper event has been detected, it is not possible to write to the General-purpose Backup registers while the
LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status register SUPC_SR.
19.2
Embedded Characteristics
8 32-bit General Purpose Backup Registers