Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

35

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin 

JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on 

page 13.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer 

to the “Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port 

is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO 

mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad 

for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAG pin and PA7 pin are used to select the JTAG Boundary Scan when asserted JTAGSEL at a high level 

and PA7 at low level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left 

unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it 

must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and 

enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. 
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be 

used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the 

“Debug and Test” Section.

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S 

series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left 

unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface 

(FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product 

datasheet.

12

ERASE

PB12

Low Level at startup

In Matrix User Interface Registers

(Refer to the System I/O 

Configuration Register in the “Bus 

Matrix” section of the datasheet.)

10

DDM

PB10

-

11

DDP

PB11

-

7

TCK/SWCLK

PB7

-

6

TMS/SWDIO

PB6

-

5

TDO/TRACESWO

PB5

-

4

TDI

PB4

-

-

PA7

 XIN32

-

See footnote 

 below

-

PA8

 XOUT32

-

-

PB9

 XIN

-

See footnote 

 below

-

PB8

 XOUT

-