Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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This command provides the system with information on the Flash organization. The system can take full 

advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so 

the software is able to adapt itself to the new configuration. 
To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR. The first word of 

the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR 

rises. The next reads of EEFC_FRR provide the following word of the descriptor. If extra read operations to 

EEFC_FRR are done after the last word of the descriptor has been returned, then EEFC_FRR value is 0 until the 

next valid command. 
 

Several commands are used to program the Flash. 
Only 0 values can be programmed using Flash technology; 1 is the erased value. In order to program words in a 

page, the page must first be erased. Commands are available to erase the full memory plane or a given number of 

pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming.
After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase 

sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands.
Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming 

command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into 

the Flash memory address space and wraps around within this Flash address space.
Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. 
32-bit words must be written continuously, in either ascending or descending order. Writing the latch buffer in a 

random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the 

data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the 

latch buffer in a continuous order.
Write operations in the latch buffer are performed with the number of wait states programmed for reading the 

Flash.
The latch buffer is automatically re-initialized, i.e., written with logical 1, after execution of each programming 

command. However, after power-up, the latch buffer is not initialized. If only part of the page is to be written with 

user data, the remaining part must be erased (written with 1).
The programming sequence is as follows:

FL_ID

0

Flash interface description

FL_SIZE

1

Flash size in bytes

FL_PAGE_SIZE

2

Page size in bytes

FL_NB_PLANE

3

Number of planes. 

FL_PLANE[0]

4

Number of bytes in the plane.

FL_NB_LOCK

4 + FL_NB_PLANE

Number of lock bits. A bit is associated 

with a lock region. A lock bit is used to 

prevent write or erase operations in the 

lock region.

FL_LOCK[0]

4 + FL_NB_PLANE + 1

Number of bytes in the first lock region.