Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
399
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
23.5
CRCCU Functional Description
23.5.1 CRC Calculation Unit
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this
CRC engine performs a checksum computation on a memory area. CRC computation is performed from the LSB
to MSB. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16 (see field description
for details).
23.5.2 CRC Calculation Unit Operation
The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA
channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL, which need to be mapped in the internal
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL, which need to be mapped in the internal
SRAM. The addresses of these two registers are pointed at by the CRCCU_DSCR.
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed
interrupt enable.
To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode Register
To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode Register
(CRCCU_MR), then configure it and finally set the DMA enable bit (DMAEN) in the CRCCU DMA Enable Register
(CRCCU_DMA_EN).
When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located
When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located
from TR_ADDR start address and computes the checksum.
The CRCCU_SR contains the temporary CRC value.
The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is
The CRCCU_SR contains the temporary CRC value.
The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is
different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In
this case, the relevant CRCCU DMA Status Register bit DMASR is automatically cleared.
If the COMPARE field of the CRCCU_MR is set to true, the TR_CRC (Transfer Reference Register) is compared
If the COMPARE field of the CRCCU_MR is set to true, the TR_CRC (Transfer Reference Register) is compared
with the last CRC computed. If a mismatch occurs, an error flag is set and an interrupt is raised (if unmasked).
The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of
The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of
the system, but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency
of the single accesses.
The CRCCU scrolls the defined memory area using ascending addresses.
In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous memory area, it is
The CRCCU scrolls the defined memory area using ascending addresses.
In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous memory area, it is
possible to re-enable the CRCCU on the new memory area and the CRC will be updated accordingly. Use the
RESET field of the CRCCU_CR to reset the CRCCU Status Register to its default value (0xFFFF_FFFF).
Table 23-1.
CRCCU Descriptor Memory Mapping
SRAM
Memory
CRCCU_DSCR+0x0
---->
TR_ADDR
CRCCU_DSCR+0x4
---->
TR_CTRL
CRCCU_DSCR+0x8
---->
Reserved
CRCCU_DSCR+0xC
---->
Reserved
CRCCU_DSCR+0x10
---->
TR_CRC