Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
42
8.1.3.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of
several consecutive pages, and each lock region has its associated lock bit.
If a locked region erase or program command occurs, the command is aborted and the EEFC triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.3.5 Security Bit
The SAM4SD32 /SD16/S16/SA16/S8 /S4/S2 feature one security bit based on a specific General Purpose NVM
bit (GPNVM bit 0). When the security bit is enabled, any access to the Flash, SRAM, core registers and internal
peripherals through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures
the confidentiality of the code programmed in the Flash.
This security bit can only be enabled through the command “Set General Purpose NVM Bit 0” of the EEFC User
This security bit can only be enabled through the command “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal
Peripherals are permitted.
The ERASE pin integrates a permanent pull-down. Consequently, it can be left unconnected during normal
The ERASE pin integrates a permanent pull-down. Consequently, it can be left unconnected during normal
operation. However, it is recommended, in harsh environment, to connect it directly to GND if the erase operation
is not used in the application.
To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in
To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in
The erase operation is not performed when the system is in Wait mode with the Flash in deep-power-down mode.
To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE
To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE
pin as GPIO or enter Wait mode with Flash in Deep-power-down mode before the ERASE pin assertion time has
elapsed.
With the following sequence, in any case, the erase operation is performed:
With the following sequence, in any case, the erase operation is performed:
1. Assert the ERASE pin (High)
2. Assert the NRST pin (Low)
3. Power cycle the device
4. Maintain the ERASE pin high for at least the minimum assertion time.
2. Assert the NRST pin (Low)
3. Power cycle the device
4. Maintain the ERASE pin high for at least the minimum assertion time.
8.1.3.6 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
Table 8-1.
Lock Bit Number
Device Name
Number of Lock Bits
Lock Region Size
SAM4SD32
256 (128 + 128)
8 Kbytes
SAM4SD16
128 (64 + 64)
8 Kbytes
SAM4S16/SA16
128
8 Kbytes
SAM4S8
64
8 Kbytes
SAM4S4
32
8 Kbytes
SAM4S2
16
8 Kbytes