Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

470

In page mode, the programming of the read timings is described in 

The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page 

access timing (t

pa

) and the NRD_PULSE for accesses to the page (t

sa

), even if the programmed value for t

pa

 is 

shorter than the programmed value for t

sa

.

The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal 

may lead to unpredictable behavior.

If the chip select and the MSB of addresses as defined in 

 are identical, then the current access lies in 

the same page as the previous one, and no page break occurs. 
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum 

access time (t

sa

 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. 

Access to D1 causes a page access with a long access time (t

pa

). Accesses to D3 and D7, though they are not 

sequential accesses, only require a short access time (t

sa

).

If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip 

select is different from the previous access, a page break occurs. If two sequential accesses are made to the page 

mode memory, but separated by an other internal or external peripheral access, a page break occurs on the 

second access because the chip select of the device was deasserted between both accesses.

READ_MODE

‘x’ No 

impact

NCS_RD_SETUP

‘x’ No

 impact

NCS_RD_PULSE

t

pa

Access time of first access to the page

NRD_SETUP

‘x’

No impact

NRD_PULSE

t

sa

Access time of subsequent accesses in the page

NRD_CYCLE

‘x’

No impact