Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
498
28.
Clock Generator
28.1
Description
The Clock Generator user interface is embedded within the Power Management Controller and is described in
. However, the Clock Generator registers are
named CKGR_.
28.2
Embedded Characteristics
The Clock Generator is made up of:
A Low-power 32768 Hz Slow Clock Oscillator with bypass mode
A Low-power RC Oscillator
A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator, which can be bypassed.
A factory-programmed Fast RC Oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default
4 MHz is selected.
Two 80 to 240 MHz programmable PLL (input from 3 to 32 MHz), capable of providing the clock MCK to the
processor and to the peripherals.
Write Protected Registers
It provides the following clocks:
SLCK, the Slow Clock, which is the only permanent clock within the system.
MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic Resonator-based
Oscillator or 4/8/12 MHz Fast RC Oscillator.
PLLACK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLA).
PLLBCK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLB).