Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

515

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The PRES field is used to control the programmable clock prescaler. It is possible to choose between 

different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES 

parameter. By default, the PRES value is set to 0 which means that PCKx is equal to slow clock.
Once PMC_PCKx register has been configured, the corresponding programmable clock must be enabled 

and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by 

polling PCKRDYx in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt 

source (PCKRDYx) has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed 

in a single write operation. 
If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be 

disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the 

programmable clock and wait for the PCKRDYx bit to be set.

9. Enable the peripheral clocks

Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled 

via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR. 

 give the worst case timings required for the master clock to switch from one selected 

clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an 

additional time of 64 clock cycles of the newly selected clock has to be added. 

Notes: 1. PLL designates either the PLLA or the PLLB Clock.

2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.

Main 

Clock

–

4 x SLCK +

2.5 x Main Clock

3 x PLL Clock +

4 x SLCK +

1 x Main Clock

SLCK

0.5 x Main Clock + 

4.5 x SLCK

–

3 x PLL Clock +

5 x SLCK

PLL Clock

0.5 x Main Clock +

4 x SLCK +

PLLCOUNT x SLCK +

2.5 x PLLx Clock

2.5 x PLL Clock +

5 x SLCK +

PLLCOUNT x SLCK

2.5 x PLL Clock +

4 x SLCK +

PLLCOUNT x SLCK