Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
55
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be
patched if a small programmable memory, for example flash, is available in the device. During initialization, the
application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table specified in the FPB configuration, which means the program in the non-
modifiable ROM can be patched.
12.2
Embedded Characteristics
Tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
̶
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing,
and code profiling.
12.3
Block Diagram
Figure 12-1.
Typical Cortex-M4 Implementation
NVIC
Debug
Access
Port
Memory
Protection Unit
Serial
Wire
Viewer
Bus Matrix
Code
Interface
SRAM and
Peripheral Interface
Data
Watchpoints
Flash
Patch
Patch
Cortex-M4
Processor
Processor
Core