Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line 

may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures 

effective optimization of the pins of the product. 
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. 
Each I/O line of the PIO Controller features:



An input change interrupt enabling level change detection on any I/O line.



Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O 

line.



A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.



A debouncing filter providing rejection of unwanted pulses from key or push button operations.



Multi-drive capability similar to an open drain I/O line.



Control of the pull-up and pull-down of the I/O line.



Input visibility and output control.

The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write 

operation.
An 8-bit parallel capture mode is also available which can be used to interface a CMOS digital image sensor, an 

ADC, a DSP synchronous port in synchronous mode, etc.



Up to 32 Programmable I/O Lines



Fully Programmable through Set/Clear Registers 



Multiplexing of Four Peripheral Functions per I/O Line



For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)

̶

Input Change Interrupt 

̶

Programmable Glitch Filter

̶

Programmable Debouncing Filter

̶

Multi-drive Option Enables Driving in Open Drain

̶

Programmable Pull-Up on Each I/O Line

̶

Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time

̶

Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-

Level

̶

Lock of the Configuration by the Connected Peripheral



Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write



Write Protect Registers



Programmable Schmitt Trigger Inputs



Parallel Capture Mode

̶

Can Be Used to Interface a CMOS Digital Image Sensor, an ADC, etc.

̶

One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines

̶

Data Can be Sampled Every Other Time (For Chrominance Sampling Only)

̶

Supports Connection of One Peripheral DMA Controller Channel (PDC) Which Offers Buffer 

Reception Without Processor Intervention