Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
568
Low-level on PIO line 3
High-level on PIO line 4
High-level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the other lines
the configuration required is described below.
31.5.10.2Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
31.5.10.3Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise,
The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise,
lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR.
31.5.10.4Falling/Rising Edge or Low/High-Level Detection Configuration
Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in
PIO_REHLSR.
The other lines are configured in falling edge or low-level detection by default if they have not been previously
The other lines are configured in falling edge or low-level detection by default if they have not been previously
configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing
32’h0000_004A in PIO_FELLSR.
Figure 31-8.
Input Change Interrupt Timings When No Additional Interrupt Modes
31.5.11 I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can
become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the
write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register (PIO_LOCKSR). Once an I/O line is locked, the
only way to unlock it is to apply a hardware reset to the PIO Controller.
31.5.12 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the
Schmitt trigger is requested when using the QTouch
™
Library.
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access